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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture
- 90 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Nonvolatile Program and Data Memories - 1K Byte In-System Programmable Flash Program Memory Endurance: 1,000 Write/Erase Cycles - 64 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program Data Security Peripheral Features - Interrupt and Wake-up on Pin Change - Two 8-bit Timer/Counters with Separate Prescalers - One 150 kHz, 8-bit High-speed PWM Output - 4-channel 10-bit ADC One Differential Voltage Input with Optional Gain of 20x - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator Special Microcontroller Features - In-System Programmable via SPI Port - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal, Calibrated 1.6 MHz Tunable Oscillator - Internal 25.6 MHz Clock Generator for Timer/Counter - External and Internal Interrupt Sources - Low-power Idle and Power-down Modes Power Consumption at 1.6 MHz, 3V, 25C - Active: 3.0 mA - Idle Mode: 1.0 mA - Power-down: < 1 A I/O and Packages - 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines Operating Voltages - 2.7V - 5.5V Internal 1.6 MHz System Clock
*
*
8-bit Microcontroller with 1K Byte Flash ATTINY15L
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*
* * *
Pin Configuration
PDIP/SOIC
(RESET/ADC0) PB5 (ADC3) PB4 (ADC2) PB3 GND 1 2 3 4 8 7 6 5 VCC PB2 (ADC1/SCK/T0/INT0) PB1 (AIN1/MISO/OC1A) PB0 (AIN0/AREF/MOSI)
Rev. 1187DS-12/01
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
1
Description
The ATTINY15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATTINY15L achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATTINY15L provides 1K byte of Flash, 64 bytes EEPROM, six general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with highspeed PWM output, internal oscillators, internal and external interrupts, programmable Watchdog Timer, 4-channel 10-bit Analog-to-Digital Converter with one differential voltage input with optional 20x gain, and three software-selectable Power-saving modes. The Idle mode stops the CPU while allowing the ADC, analog comparator, Timer/Counters and interrupt system to continue functioning. The ADC Noise Reduction mode facilitates high-accuracy ADC measurements by stopping the CPU while allowing the ADC to continue functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATTINY15L to be highly responsive to external events, still featuring the lowest power consumption while in the Power-saving modes. The device is manufactured using Atmel's high-density, nonvolatile memory technology. By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATTINY15L is a powerful microcontroller that provides a highly flexible and cost-efficient solution to many embedded control applications. The peripheral features make the ATTINY15L particularly suited for battery chargers, lighting ballasts and all kinds of intelligent sensor applications. The ATTINY15L AVR is supported with a full suite of program and system development tools including macro assemblers, program debugger/simulators, In-circuit emulators and evaluation kits.
2
ATTINY15L
1187DS-12/01
ATTINY15L
Block Diagram
Figure 1. The ATTINY15L Block Diagram
VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL
TUNABLE INTERNAL OSCILLATOR
PROGRAM FLASH
HARDWARE STACK
MCU CONTROL REGISTER
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
MCU STATUS REGISTER
INSTRUCTION DECODER
Z
TIMER/ COUNTER0
CONTROL LINES
ALU
TIMER/ COUNTER1
STATUS REGISTER
INTERRUPT UNIT
PROGRAMMING LOGIC
ISP MODULE
DATA EEPROM
ANALOG MUX
ADC
ANALOG COMPARATOR
DATA REGISTER PORT B
DATA DIR. REG.PORT B
+ -
PORT B DRIVERS
PB0-PB5
3
1187DS-12/01
Pin Descriptions
VCC GND Port B (PB5..PB0) Supply voltage pin. Ground pin. Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse and the special function associated with this pin is external Reset. The port pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also accommodates analog I/O pins. The Port B pins with alternate functions are shown in Table 1. Table 1. Port B Alternate Functions
Port Pin PB0 Alternate Function MOSI (Data Input Line for Memory Downloading) AREF (ADC Voltage Reference) AIN0 (Analog Comparator Positive Input) MISO (Data Output Line for Memory Downloading) OC1A (Timer/Counter PWM Output) AIN1 (Analog Comparator Negative Input) SCK (Serial Clock Input for Serial Programming) INT0 (External Interrupt0 Input) ADC1 (ADC Input Channel 1) T0 (Timer/Counter0 External Counter Input) ADC2 (ADC Input Channel 2) ADC3 (ADC Input Channel 3) RESET (External Reset Pin) ADC0 (ADC Input Channel 0)
PB1
PB2
PB3 PB4 PB5
Analog Pins
Up to four analog inputs can be selected as inputs to Analog-to-Digital Converter (ADC). The internal oscillator provides a clock rate of nominally 1.6 MHz for the system clock (CK). Due to large initial variation (0.8 -1.6 MHz) of the internal oscillator, a tuning capability is built in. Through an 8-bit control register - OSCCAL - the system clock rate can be tuned with less than 1% steps of the nominal clock. There is an internal PLL that provides a 16x clock rate locked to the system clock (CK) for the use of the Peripheral Timer/Counter1. The nominal frequency of this peripheral clock, PCK, is 25.6 MHz.
Internal Oscillators
4
ATTINY15L
1187DS-12/01
ATTINY15L
ATTINY15L Register Summary
Address
$3F $3E $3C $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 $31 $30 $2F $2E $2D $2C $2B $2A $29 $28 $27 $26 $25 $24 $23 $22 $21 $20 $1F $1E $1D $1C $1B $1A $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $0F $0E $0D $0C $0B $0A $09 $08 $07 $06 $05 $04 ... $00
Name
SREG Reserved Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 OSCCAL TCCR1 TCNT1 OCR1A OCR1B SFIOR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACSR ADMUX ADCSR ADCH ADCL Reserved Reserved
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
page 11
-
INT0 INTF0 OCIE1A OCF1A
PCIE PCIF -
-
-
TOIE1 TOV1
TOIE0 TOV0
-
page 19 page 19 page 20 page 21
-
PUD -
SE -
SM1 -
SM0 WDRF -
BORF CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
page 22 page 17 page 27 page 28 page 24
Timer/Counter0 (8-Bit) Oscillator Calibration Register CTC1 PWM1 COM1A1 COM1A0 CS13 CS12 CS11 CS10 Timer/Counter1 (8-Bit) Timer/Counter1 Output Compare Register A (8-Bit) Timer/Counter1 Output Compare Register B (8-Bit) FOC1A PSR1 PSR0
page 30 page 31 page 31 page 33 page 26
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
page 34
-
-
EEAR5 -
EEAR4 -
EEAR3 EERIE
EEAR2 EEMWE
EEAR1 EEWE
EEAR0 EERE
page 36 page 36 page 36
EEPROM Data Register (8-Bit)
-
-
DDB5 PINB5
PORTB4 DDB4 PINB4
PORTB3 DDB3 PINB3
PORTB2 DDB2 PINB2
PORTB1 DDB1 PINB1
PORTB0 DDB0 PINB0
page 51 page 51 page 51
ACD REFS1 ADEN
ACBG REFS0 ADSC
ACO ADLAR ADFR
ACI ADIF
ACIE ADIE
MUX2 ADPS2
ACIS1 MUX1 ADPS1
ACIS0 MUX0 ADPS0
page 39 page 46 page 47 page 48 page 48
ADC Data Register High Byte ADC Data Register Low Byte
5
1187DS-12/01
ATTINY15L Instruction Set Summary
Mnemonic
ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP RCALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID LD ST MOV LDI IN OUT LPM BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register I/O(P,b) 1 None 2 Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Rd, Z Z, Rr Rd, Rr Rd, K Rd, P P, Rr
Operands
Rd, Rr Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k k
Description
Add Two Registers Add with Carry Two Registers Subtract Two Registers Subtract Constant from Register Subtract with Carry Two Registers Subtract with Carry Constant from Reg. Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Relative Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half-carry Flag Set Branch if Half-carry Flag Cleared Branch if T-flag Set Branch if T-flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Load Register Indirect Store Register Indirect Move between Registers Load Immediate In Port Out Port Load Program Memory
Operation
Rd Rd + Rr Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd RdRr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * (FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd RdRd Rd $FF PC PC + k + 1 PC PC + k + 1 PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 Rd (Z) (Z) Rr Rd Rr Rd K Rd P P Rr R0 (Z)
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
# Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 1 3
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
6
ATTINY15L
1187DS-12/01
ATTINY15L
ATTINY15L Instruction Set Summary (Continued)
Mnemonic
CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR
Operands
P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Description
Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset
Operation
I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer)
Flags
None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None
# Clocks
2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7
1187DS-12/01
Ordering Information
Power Supply 2.7 - 5.5V Speed (MHz) 1.6 Ordering Code ATTINY15L-1PC ATTINY15L-1SC ATTINY15L-1PI ATTINY15L-1SI Package 8P3 8S2 8P3 8S2 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 8P3 8S2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8
ATTINY15L
1187DS-12/01
ATTINY15L
Packaging Information
8P3
8P3, 8-lead, Plastic Dual Inline Package (PDIP), 0.300" Wide. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-001 BA 10.16(0.400) 9.017(0.355) PIN 1 7.11(0.280) 6.10(0.240)
.300 (7.62) REF
254(0.100) BSC 5.33(0.210) MAX Seating Plane 3.81(0.150) 2.92(0.115) 1.78(0.070) 1.14(0.045) 4.95(0.195) 2.92(0.115)
0.381(0.015)MIN 0.559(0.022) 0.356(0.014)
8.26(0.325) 7.62(0.300) 0.356(0.014) 0.203(0.008)
1.524(0.060) 0.000(0.000) 10.90(0.430) MAX *Controlling dimension: Inches
REV. A
04/11/2001
9
1187DS-12/01
8S2
.020 (.508) .012 (.305)
PIN 1
.213 (5.41) .205 (5.21)
.330 (8.38) .300 (7.62)
.050 (1.27) BSC
.212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78)
.013 (.330) .004 (.102) 0 REF 8 .035 (.889) .020 (.508) .010 (.254) .007 (.178)
10
ATTINY15L
1187DS-12/01
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1187DS-12/01/0M

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